MC9S08JM16 Datasheet, PDF (303/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Universal Serial Bus Device Controller (S08USBV1)
Table 17-7. REV Field Descriptions
Field
8–0
REV[7:0]
Description
Revision — Revision number of the USB module.
17.3.5 Interrupt Status Register (INTSTAT)
The INTSTAT contains bits for each of the interrupt source within the USB module. Each of these bits is
qualified with its respective interrupt enable bits (see the interrupt enable register). All bits of the register
are logically OR'ed together to form a single interrupt source for the microcontroller. Once an interrupt bit
has been set, it may only be cleared by writing a 1 to the respective interrupt bit. This register will contain
the value of 0x00 after a reset.
R
W
Reset
7
STALLF
0
6
5
4
3
2
0
RESUMEF SLEEPF TOKDNEF SOFTOKF
0
0
0
0
0
= Unimplemented or Reserved
Figure 17-8. Interrupt Status Register (INTSTAT)
1
ERRORF
0
0
USBRSTF
0
Table 17-9. INTSTAT Field Descriptions
Field
Description
7
STALLF
Stall Flag — The stall interrupt is used in device mode. In device mode the stall flag is asserted when a STALL
handshake is sent by the serial interface engine (SIE).
0 A STALL handshake has not been sent
1 A STALL handshake has been sent
5
RESUMEF
Resume Flag — This bit is set 2.5 μs after clocks to the USB module have restarted following resume signaling.
It can be used to indicate remote wakeup signaling on the USB bus. This interrupt is enabled only when the
USB module is about to enter suspend mode (usually when SLEEPF interrupt detected).
0 No RESUME observed
1 RESUME detected (K-state is observed on the USBDP/USBDN signals for 2.5 μs)
4
SLEEPF
Sleep Flag — This bit is set if the USB module has detected a constant idle on the USB bus for 3 ms, indicating
that the USB module will go into suspend mode. The sleep timer is reset by activity on the USB bus.
0 No constant idle state of 3 ms has been detected on the USB bus
1 A constant idle state of 3 ms has been detected on the USB bus
3
TOKDNEF
Token Complete Flag — This bit is set when the current transaction is completed. The firmware must
immediately read the STAT register to determine the endpoint and BD information. Clearing this bit (by setting it
to 1) causes the STAT register to be cleared or the STAT FIFO holding register to be loaded into the STAT register.
0 No tokens being processed are complete
1 Current token being processed is complete
2
SOF Token Flag — This bit is set if the USB module has received a start of frame (SOF) token.
SOFTOKF 0 The USB module has not received an SOF token
1 The USB module has received an SOF token
MC9S08JM16 Series Data Sheet, Rev. 2
Freescale Semiconductor
303