MC9S08JM16 Datasheet, PDF (363/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
3 _{This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE,}
BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
4 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.}
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via V_DD and V_SS and variation in crystal oscillator frequency increase the C_Jitter percentage for a given
interval.
5 _{Jitter measurements are based upon a 48 MHz MCGOUT clock frequency.}
6 _{Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG}
is already in lock, then the MCG may stay in lock.
7 _{Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.}
A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1 Control Timing
Table A-12. Control Timing
Num C
Parameter
Symbol
Min
Typical¹
Max
Unit
1
Bus frequency (t_cyc = 1/f_Bus)
f_Bus
DC
—
24
MHz
2
Internal low-power oscillator period
3
External reset pulse width²
t_LPO
700
t_extrst
100
1300
μs
—
ns
4
Reset low drive
t_rstdrv
66 × t_cyc
—
ns
5
Active background debug mode latch setup time
t_MSSU
500
—
ns
6
Active background debug mode latch hold time
t_MSH
100
—
ns
7
IRQ pulse width
Asynchronous path²
Synchronous path³
t_ILIH, t_IHIL
100
—
1.5 × t_cyc
—
ns
8
KBIPx pulse width
Asynchronous path²
Synchronous path³
t_ILIH, t_IHIL
100
—
1.5 x t_cyc
—
ns
9
Port rise and fall time
low output drive (PTxDS = 0),(load = 50 pF)⁴
Slew rate control disabled (PTxSE = 0)
—
40
Slew rate control enabled (PTxSE = 1) t_Rise, t_Fall
75
ns
high output drive (PTxDS = 1), (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
—
11
Slew rate control enabled (PTxSE = 1)
35
1 _{Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.}
2 _{This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to}
override reset requests from internal sources.
3 _{This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or}
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 85 °C.}
MC9S08JM16 Series Data Sheet, Rev. 2
Freescale Semiconductor
363