MC9S08JM16 Datasheet, PDF (68/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 Resets, Interrupts, and System Configuration
5.6.3 LVD Interrupt Operation
When a low voltage condition is detected and the LVD circuit is configured for interrupt operation (LVDE
set, LVDIE set, and LVDRE clear), then LVDF will be set and an LVD interrupt will occur.
5.6.4 Low-Voltage Warning (LVW)
The LVD system has a low voltage warning flag to indicate the user that the supply voltage is approaching,
but is still above, the LVD voltage. The LVW does not have an interrupt associated with it. There are two
user selectable trip voltages for the LVW, one high (V_LVWH) and one low (V_LVWL). The trip voltage is
selected by LVWV in SPMSC2.
5.7 Reset, Interrupt, and System Control Registers and Control Bits
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to the direct-page register summary in Chapter 4, “Memory,” of this data sheet for the absolute
address assignments for all registers. This section refers to registers and control bits only by their names.
A Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, “Modes of Operation.”
5.7.1 Interrupt Pin Request Status and Control Register (IRQSC)
This direct-page register includes status and control bits, which are used to configure the IRQ function,
report status, and acknowledge IRQ events.
R
W
Reset
7
6
5
4
3
2
1
0
IRQF
0
IRQPDD IRQEDG
IRQPE
IRQIE
IRQACK
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-2. Interrupt Request Status and Control Register (IRQSC)
0
IRQMOD
0
MC9S08JM16 Series Data Sheet, Rev. 2
68
Freescale Semiconductor