MC9S08JM16 Datasheet, PDF (34/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 3 Modes of Operation
For the ACMP to operate when ACGBS in ACMPSC is set, the LVD must be left enabled when entering
stop3.
For the XOSC to operate with an external reference when RANGE in MCGC2 is set, the LVD must be left
enabled when entering stop3.
3.6.1.2 Active BDM Enabled in Stop Mode
Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This
register is described in Chapter 18, “Development Support.” If ENBDM is set when the CPU executes a
STOP instruction, the system clocks to the background debug logic remain active when the MCU enters
stop mode. Because of this, background debug communication remains possible. In addition, the voltage
regulator does not enter its low-power standby state but maintains full internal regulation. If the user
attempts to enter stop2 with ENBDM set, the MCU will enter stop3 instead.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After entering background debug mode, all background
commands are available.
3.6.2 Stop2 Mode
Stop2 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most
of the internal circuitry of the MCU is powered off in stop2, with the exception of the RAM. Upon entering
stop2, all I/O pin control signals are latched so that the pins retain their states during stop2.
Exit from stop2 is performed by asserting either wake-up pin: RESET or IRQ.
NOTE
IRQ/TPMCLK always functions as an active-low wakeup input when the
MCU is in stop2, regardless of how the pin is configured before entering
stop2. The pullup on this pin is always disabled in stop2. This pin must be
driven or pulled high externally while in stop2 mode.
In addition, the RTC interrupt can wake the MCU from stop2, if enabled.
Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR):
• All module control and status registers are reset
• The LVD reset function is enabled and the MCU remains in the reset state if V_DD is below the LVD
trip point (low trip point selected due to POR)
• The CPU takes the reset vector
In addition to the above, upon waking up from stop2, the PPDF bit in SPMSC2 is set. This flag is used to
direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched
until a 1 is written to PPDACK in SPMSC2.
MC9S08JM16 Series Data Sheet, Rev. 2
34
Freescale Semiconductor