MC9S08JM16 Datasheet, PDF (204/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Multi-Purpose Clock Generator (S08MCGV1)
c) MCGC1 = 0x98 (%10011000)
– RDIV (bits 5-3) set to %011, or divide-by-8 because 8 MHz / 8= 1 MHz which is in the 1
MHz to 2 MHz range required by the PLL. In BLPE mode, the configuration of the RDIV
does not matter because both the FLL and PLL are disabled. Changing them only sets up the
the dividers for PLL usage in PBE mode
d) MCGC3 = 0x44 (%01000100)
– PLLS (bit 6) set to 1, selects the PLL. In BLPE mode, changing this bit only prepares the
MCG for PLL usage in PBE mode
– VDIV (bits 3-0) set to %0100, or multiply-by-16 because 1 MHz reference * 16 = 16 MHz.
In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is
disabled. Changing them only sets up the multiply value for PLL usage in PBE mode
e) Loop until PLLST (bit 5) in MCGSC is set, indicating that the current source for the PLLS
clock is the PLL
3. Then, BLPE mode transitions into PBE mode:
a) Clear LP (bit 3) in MCGC2 to 0 here to switch to PBE mode
b) Then loop until LOCK (bit 6) in MCGSC is set, indicating that the PLL has acquired lock
4. Last, PBE mode transitions into PEE mode:
a) MCGC1 = 0x18 (%00011000)
– CLKS (bits7 and 6) in MCGSC1 set to %00 in order to select the output of the PLL as the
system clock source
– Loop until CLKST (bits 3 and 2) in MCGSC are %11, indicating that the PLL output is
selected to feed MCGOUT in the current clock mode
b) Now, With an RDIV of divide-by-8, a BDIV of divide-by-1, and a VDIV of multiply-by-16,
MCGOUT = [(8 MHz / 8) × 16] / 1 = 16 MHz, and the bus frequency is MCGOUT / 2, or 8
MHz
MC9S08JM16 Series Data Sheet, Rev. 2
204
Freescale Semiconductor