MC9S08JM16 Datasheet, PDF (143/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (S08ADC12V1)
10.3.6 Compare Value Low Register (ADCCVL)
This register holds the lower 8 bits of the 12-bit or 10-bit compare value or all 8 bits of the 8-bit compare
value. When the compare function is enabled, bits ADCV[7:0] are compared to the lower 8 bits of the
result following a conversion in 12-bit, 10-bit or 8-bit mode.
7
R
ADCV7
W
Reset:
0
6
ADCV6
5
ADCV5
4
ADCV4
3
ADCV3
2
ADCV2
1
ADCV1
0
0
0
0
0
0
Figure 10-8. Compare Value Low Register (ADCCVL)
0
ADCV0
0
10.3.7 Configuration Register (ADCCFG)
ADCCFG selects the mode of operation, clock source, clock divide, and configures for low power and long
sample time.
7
R
ADLPC
W
Reset:
0
6
5
ADIV
4
ADLSMP
3
2
MODE
0
0
0
0
0
Figure 10-9. Configuration Register (ADCCFG)
1
0
ADICLK
0
0
Table 10-6. ADCCFG Register Field Descriptions
Field
Description
7
ADLPC
6:5
ADIV
4
ADLSMP
3:2
MODE
1:0
ADICLK
Low-Power Configuration. ADLPC controls the speed and power configuration of the successive approximation
converter. This optimizes power consumption when higher sample rates are not required.
0 High speed configuration
1 Low power configuration:The power is reduced at the expense of maximum clock speed.
Clock Divide Select. ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK.
Table 10-7 shows the available clock configurations.
Long Sample Time Configuration. ADLSMP selects between long and short sample time. This adjusts the
sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for
lower impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
0 Short sample time
1 Long sample time
Conversion Mode Selection. MODE bits are used to select between 12-, 10-, or 8-bit operation. See Table 10-8.
Input Clock Select. ADICLK bits select the input clock source to generate the internal clock ADCK. See
Table 10-9.
MC9S08JM16 Series Data Sheet, Rev. 2
Freescale Semiconductor
143