MC9S08JM16 Datasheet, PDF (157/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (S08ADC12V1)
• There is no I/O switching, input or output, on the MCU during the conversion.
There are some situations where external system activity causes radiated or conducted noise emissions or
excessive V_DD noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in
wait or stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise
on the accuracy:
• Place a 0.01 μF capacitor (C_AS) on the selected input channel to V_REFL or V_SSAD (this improves
noise issues, but affects the sample rate based on the external analog source resistance).
• Average the result by converting the analog input many times in succession and dividing the sum
of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error.
• Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and
averaging. Noise that is synchronous to ADCK cannot be averaged out.
10.6.2.4 Code Width and Quantization Error
The ADC quantizes the ideal straight-line transfer function into 4096 steps (in 12-bit mode). Each step
ideally has the same height (1 code) and width. The width is defined as the delta between the transition
points to one code and the next. The ideal code width for an N bit converter (in this case N can be 8, 10 or
12), defined as 1LSB, is:
1 lsb = (V_REFH – V_REFL) / 2^N
Eqn. 10-2
There is an inherent quantization error due to the digitization of the result. For 8-bit or 10-bit conversions
the code transitions when the voltage is at the midpoint between the points where the straight line transfer
function is exactly represented by the actual transfer function. Therefore, the quantization error will be
±1/2 lsb in 8- or 10-bit mode. As a consequence, however, the code width of the first (0x000) conversion
is only 1/2 lsb and the code width of the last (0xFF or 0x3FF) is 1.5 lsb.
For 12-bit conversions the code transitions only after the full code width is present, so the quantization
error is −1 lsb to 0 lsb and the code width of each step is 1 lsb.
10.6.2.5 Linearity Errors
The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these
errors but the system must be aware of them because they affect overall accuracy. These errors are:
• Zero-scale error (E_ZS) (sometimes called offset) — This error is defined as the difference between
the actual code width of the first conversion and the ideal code width (1/2 lsb in 8-bit or 10-bit
modes and 1 lsb in 12-bit mode). If the first conversion is 0x001, the difference between the actual
0x001 code width and its ideal (1 lsb) is used.
• Full-scale error (E_FS) — This error is defined as the difference between the actual code width of
the last conversion and the ideal code width (1.5 lsb in 8-bit or 10-bit modes and 1LSB in 12-bit
mode). If the last conversion is 0x3FE, the difference between the actual 0x3FE code width and its
ideal (1LSB) is used.
• Differential non-linearity (DNL) — This error is defined as the worst-case difference between the
actual code width and the ideal code width for all conversions.
MC9S08JM16 Series Data Sheet, Rev. 2
Freescale Semiconductor
157