MC9S08JM16 Datasheet, PDF (188/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Multi-Purpose Clock Generator (S08MCGV1)
12.4 Functional Description
12.4.1 Operational Modes
IREFS=1
CLKS=00
PLLS=0
FLL Engaged
Internal (FEI)
IREFS=1
CLKS=01
PLLS=0
BDM Enabled
or LP=0
FLL Bypassed
Internal (FBI)
Bypassed
IREFS=1
Low Power
CLKS=01 _{Internal (BLPI)}
BDM Disabled
and LP=1
FLL Engaged
External (FEE)
IREFS=0
CLKS=00
PLLS=0
FLL Bypassed
External (FBE)
IREFS=0
CLKS=10
PLLS=0
BDM Enabled
or LP=0
IREFS=0
CLKS=10
BDM Disabled
and LP=1
Bypassed
Low Power
External (BLPE)
PLL Bypassed
External (PBE)
IREFS=0
CLKS=10
PLLS=1
BDM Enabled
or LP=0
PLL Engaged IREFS=0
External (PEE) CLKS=00
PLLS=1
Entered from any state
when MCU enters stop
Stop
Returns to state that was active
before MCU entered stop, unless
RESET occurs while in stop.
Figure 12-8. Clock Switching Modes
The nine states of the MCG are shown as a state diagram and are described below. The arrows indicate the
allowed movements between the states.
12.4.1.1 FLL Engaged Internal (FEI)
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
conditions occur:
• CLKS bits are written to 00
• IREFS bit is written to 1
• PLLS bit is written to 0
• RDIV bits are written to 000. Because the internal reference clock frequency must already be in
the range of 31.25 kHz to 39.0625 kHz after it is trimmed, no further frequency divide is necessary.
MC9S08JM16 Series Data Sheet, Rev. 2
188
Freescale Semiconductor