MC68HC705P9 Datasheet, PDF (90/160 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O) Ports
Writing a logic one to a DDRC bit enables the output buffer for the
corresponding port C pin; a logic zero disables the output buffer.
When bit DDRCx is a logic one, reading address $0002 reads the PCx
data latch. When bit DDRCx is a logic zero, reading address $0002
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 7-3 summarizes the
operation of the port C pins.
Table 7-3. Port C Pin Operation
Accesses to Data Bit
Data Direction Bit I/O Pin Mode
Read
Write
0
Input, Hi-Z⁽¹⁾
Pin
Latch⁽²⁾
1
Output
Latch
Latch
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
7.6 Port D
Port D is a 2-bit port with one I/O pin and one input-only pin. Port D
shares the input-only pin, PD7/TCAP, with the capture/compare timer.
PD7/TCAP is the timer input capture pin. The PD7/TCAP pin can always
be a general-purpose input, even if input capture interrupts are enabled.
Technical Data
90
Parallel Input/Output (I/O) Ports
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MC68HC705P9 — Rev. 4.0
MOTOROLA