MC68HC705P9 Datasheet, PDF (69/160 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Resets and Interrupts
Interrupts
5.4.1 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
5.4.2 External Interrupt
An interrupt signal on the IRQ/V_PP pin latches an external interrupt
request. When the CPU completes its current instruction, it tests the IRQ
latch. If the IRQ latch is set, the CPU then tests the I bit in the condition
code register. If the I bit is clear, the CPU then begins the interrupt
sequence.
The CPU clears the IRQ latch during interrupt processing, so that
another interrupt signal on the IRQ/V_PP pin can latch another interrupt
request during the interrupt service routine. As soon as the I bit is cleared
during the return from interrupt, the CPU can recognize the new interrupt
request. Figure 5-4 shows the IRQ/V_PP pin interrupt logic.
IRQ/V_PP
LEVEL-SENSITIVE TRIGGER
(MOR OPTION)
V_DD
D
Q
CK
CLR
(FROM CCR)
I
Figure 5-4. External Interrupt Logic
EXTERNAL
INTERRUPT
REQUEST
RESET
VECTOR FETCH
Setting the I bit in the condition code register disables external interrupts.
Interrupt triggering sensitivity of the IRQ/V_PP pin is a programmable
option. The IRQ/V_PP pin can be negative-edge triggered or negative-
edge- and low-level triggered. The level-sensitive triggering option
allows multiple external interrupt sources to be wire-ORed to the
MC68HC705P9 — Rev. 4.0
MOTOROLA
Resets and Interrupts
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Technical Data
69