MC68HC705P9 Datasheet, PDF (84/160 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O) Ports
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 7-4 shows the I/O logic of port A.
READ DATA DIRECTION REGISTER A ($0004)
WRITE DATA DIRECTION REGISTER A ($0004)
RESET
DDRAx
WRITE PORT A DATA REGISTER ($0000)
PAx
PAx
READ PORT A DATA REGISTER ($0000)
Figure 7-4. Port A I/O Circuit
Writing a logic one to a DDRA bit enables the output buffer for the
corresponding port A pin; a logic zero disables the output buffer.
When bit DDRAx is a logic one, reading address $0000 reads the PAx
data latch. When bit DDRAx is a logic zero, reading address $0000
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 7-1 summarizes the
operation of the port A pins.
Table 7-1. Port A Pin Operation
Accesses to Data Bit
Data Direction Bit I/O Pin Mode
Read
Write
0
Input, Hi-Z⁽¹⁾
Pin
Latch⁽²⁾
1
Output
Latch
Latch
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
Technical Data
84
Parallel Input/Output (I/O) Ports
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MC68HC705P9 — Rev. 4.0
MOTOROLA