MC68HC705P9 Datasheet, PDF (72/160 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Resets and Interrupts
5.4.4 Interrupt Processing
The CPU takes the following actions to begin servicing an interrupt:
• Stores the CPU registers on the stack in the order shown in
Figure 5-6
• Sets the I bit in the condition code register to prevent further
interrupts
• Loads the program counter with the contents of the appropriate
interrupt vector locations:
– $1FFC and $1FFD (software interrupt vector)
– $1FFA and $1FFB (external interrupt vector)
– $1FF8 and $1FF9 (timer interrupt vector)
The return from interrupt (RTI) instruction causes the CPU to recover the
CPU registers from the stack as shown in Figure 5-6.
UNSTACKING
•
ORDER
•
•
$00C0 (BOTTOM OF STACK)
$00C1
$00C2
•
•
•
5
1
4
2
3
3
2
4
1
5
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
STACKING
ORDER
•
•
•
•
•
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 5-6. Interrupt Stacking Order
Technical Data
72
Resets and Interrupts
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MC68HC705P9 — Rev. 4.0
MOTOROLA