MC68HC705P9 Datasheet, PDF (125/160 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Serial Input/Output Port (SIOP)
Interrupts
10.6 Interrupts
The SIOP does not generate interrupt requests.
10.7 I/O Registers
The following registers control and monitor SIOP operation:
• SIOP control register (SCR)
• SIOP status register (SSR)
• SIOP data register (SDR)
10.7.1 SIOP Control Register
The read/write SIOP control register (SCR) contains two bits. One bit
enables the SIOP, and the other configures the SIOP for master mode
or for slave mode.
$000A Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
SPE
0
MSTR
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 10-6. SIOP Control Register (SCR)
SPE — SIOP Enable
This read/write bit enables the SIOP. Setting SPE initializes the data
direction register as follows:
• The PB6/SDI pin is an input.
• The PB5/SDO pin is an output.
• The PB7/SCK pin is an input in slave mode and an output in
master mode.
Clearing SPE disables the SIOP and returns the port to its normal I/O
functions. The data direction register and the port data register remain
in their SIOP-initialized state.
NOTE: After clearing SPE, be sure to initialize the port for its intended I/O use.
MC68HC705P9 — Rev. 4.0
MOTOROLA
Serial Input/Output Port (SIOP)
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Technical Data
125