MC68HC705P9 Datasheet, PDF (112/160 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Timer
Freescale Semiconductor, Inc.
9.7.3 Timer Registers
The read-only timer registers (TRH and TRL) contain the current high
and low bytes of the 16-bit counter. Reading TRH before reading TRL
causes TRL to be latched until TRL is read. Reading TRL after reading
the timer status register clears the timer overflow flag (TOF). Writing to
the timer registers has no effect.
$0018
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Reset initializes TRH to $FF
$0019
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Reset initializes TRL to $FC
= Unimplemented
Figure 9-12. Timer Registers (TRH and TRL)
Reading TRH returns the current value of the high byte of the counter
and causes the low byte to be latched into a buffer. The buffer value
remains fixed even if the high byte is read more than once. Reading TRL
reads the transparent low byte buffer and completes the read sequence
of the timer registers.
INTERNAL
DATA BUS
LATCH
BUFFER
READ TRH
TRH ($0018)
TRL ($0019)
Figure 9-13. Timer Register Reads
NOTE:
To prevent interrupts from occurring between readings of TRH and TRL,
set the interrupt mask (I bit) in the condition code register before reading
TRH, and clear the mask after reading TRL.
Technical Data
112
Timer
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MC68HC705P9 — Rev. 4.0
MOTOROLA