MC68HC705P9 Datasheet, PDF (48/160 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
4.6.4 Program Counter
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched. The three most significant bits
of the program counter are ignored internally and appear as 000.
Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2
Read:
Write:
Reset: 0 0 0
Loaded with vector from $1FFE and $1FFF
Figure 4-5. Program Counter (PC)
Bit
10
4.6.5 Condition Code Register
The condition code register is an 8-bit register whose three most
significant bits are permanently fixed at 111. The condition code register
contains the interrupt mask and four flags that indicate the results of the
instruction just executed.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
1
1
1
H
I
N
Z
C
Write:
Reset:
1
1
1
U
1
U
U
U
= Unimplemented
U = Unaffected
Figure 4-6. Condition Code Register (CCR)
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an ADD or ADC operation. The half-
carry flag is required for binary-coded decimal (BCD) arithmetic
operations.
Technical Data
48
Central Processor Unit (CPU)
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MC68HC705P9 — Rev. 4.0
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