MC68HC705P9 Datasheet, PDF (80/160 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Low Power Modes
Figure 6-4 shows the effect of the STOP and WAIT instructions on the
CPU clock and the timer clock.
OSC1
OSC2
WAIT
STOP
INTERNAL
OSCILLATOR
÷ 2 ^{INTERNAL CLOCK}
÷2
CPU CLOCK
TIMER CLOCK
ADC CLOCK
Figure 6-4. STOP/WAIT Clock Logic
6.4 Data-Retention Mode
In data-retention mode, the MCU retains RAM contents and CPU
register contents at V_DD voltages as low as 2.0 Vdc. The data-retention
feature allows the MCU to remain in a low-power consumption state
during which it retains data, but the CPU cannot execute instructions.
To put the MCU in data-retention mode:
1. Drive the RESET pin to logic zero.
2. Lower the V_DD voltage. The RESET pin must remain low
continuously during data-retention mode.
To take the MCU out of data-retention mode:
1. Return V_DD to normal operating voltage.
2. Return the RESET pin to logic one.
Technical Data
80
Low Power Modes
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MC68HC705P9 — Rev. 4.0
MOTOROLA