MC68HC705P9 Datasheet, PDF (135/160 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
I/O Registers
When the internal RC oscillator is being used as the ADC clock, two
limitations apply:
• Because of the frequency tolerance of the RC oscillator and its
asynchronism with the internal clock, the conversion complete flag
must be used to determine when a conversion sequence is
complete.
• The conversion process runs at the nominal 1.5-MHz rate, but the
conversion results must be transferred to the ADC data register
synchronously with the internal clock; therefore, the conversion
process is limited to a maximum of one channel every internal
clock cycle.
ADON — ADC On
This read/write bit turns on the ADC. When the ADC is on, it requires
a time, t_ADON, for the current sources to stabilize. During this time,
results can be inaccurate. Resets clear the ADON bit.
1 = ADC turned on
0 = ADC turned off
Bits 4–2 — Not used
Bits 4–2 always read as logic zeros.
CH[2:0] — Channel Select Bits
These read/write bits select one of eight ADC input channels as
shown in Table 11-2. Channels 0–3 are the input pins, PC3/AN3,
PC4/AN2, PC5/AN1, and PC6/AN0. Channels 4–6 can be used for
reference measurements. Channel 7 is reserved for factory testing.
Table 11-2. ADC Input Channel Selection
CH[2:1:0]
000
001
010
011
100
101
110
111
Channel
0
1
2
3
4
5
6
7
Signal
AN0
AN1
AN2
AN3
V_RH
(V_RH + V_SS) / 2
V_SS
Reserved
MC68HC705P9 — Rev. 4.0
MOTOROLA
Analog-to-Digital Converter (ADC)
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Technical Data
135