MC68HC705P9 Datasheet, PDF (67/160 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Resets and Interrupts
Resets
V_DD
(NOTE 1)
OSC1 PIN
4064 t_CYC
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
1FFE 1FFE 1FFE 1FFE 1FFE 1FFE 1FFF
INTERNAL
DATA BUS
NEW
NEW
PCH
PCL
Notes:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 5-2. Power-On Reset Timing
5.2.2 External Reset
A logic zero applied to the RESET pin for one and one-half t_CYC
generates an external reset. A Schmitt trigger senses the logic level at
the RESET pin.
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
1FFE 1FFE 1FFE 1FFE 1FFF NEW PC NEW PC
INTERNAL
DATA BUS
t_RL
RESET
NEW
PCH
NEW
PCL
DUMMY
OP
CODE
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 5-3. External Reset Timing
Table 5-1. External Reset Timing
Characteristic
RESET Pulse Width
Symbol Min
t_RL
1.5
Max
—
Unit
t_CYC
MC68HC705P9 — Rev. 4.0
MOTOROLA
Resets and Interrupts
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Technical Data
67