MC68HC705P9 Datasheet, PDF (36/160 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Memory
Freescale Semiconductor, Inc.
Addr.
$001D
$001E
$001F
Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
6
ADC Data Register
(ADDR) Write:
See page 136.
Reset:
5
4
3
2
Unaffected by reset
1
Bit 0
Read: CCF
0
ADC Status/Control Register
ADRC ADON
(ADSCR) Write:
See page 134.
Reset: 0
0
0
0
0
CH2 CH1 CH0
0
0
0
0
Reserved Read: R
R
R
R
R
R
R
R
$0900
$1FF0
Read: 0
0
0
0
0
SIOP IRQ COPE
Mask Option Register
(MOR) Write:
See page 42.
Reset:
Unaffected by reset
0
Read:
COP Register
R
R
R
R
R
R
R COPC
(COPR) Write:
See page 97.
Reset:
Unaffected by reset
= Unimplemented
R = Reserved
Figure 3-2. I/O Register Summary (Sheet 4 of 4)
U = Unaffected
3.5 RAM
The 128 addresses from $0080–$00FF are RAM locations. The CPU
uses the top 64 RAM addresses, $00C0–$00FF, as the stack. Before
processing an interrupt, the CPU uses five bytes of the stack to save the
contents of the CPU registers. During a subroutine call, the CPU uses
two bytes of the stack to store the return address. The stack pointer
decrements when the CPU stores a byte on the stack and increments
when the CPU retrieves a byte from the stack.
NOTE:
Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
Technical Data
36
Memory
For More Information On This Product,
Go to: www.freescale.com
MC68HC705P9 — Rev. 4.0
MOTOROLA