MC68HC705P9 Datasheet, PDF (126/160 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Serial Input/Output Port (SIOP)
Clearing SPE during a transmission aborts the transmission, resets
the bit counter, and returns the port to its normal I/O function. Reset
clears SPE.
1 = SIOP enabled
0 = SIOP disabled
MSTR — Master Mode Select
This read/write bit configures the SIOP for master mode. Setting
MSTR initializes the PB7/SCK pin as the serial clock output. Clearing
MSTR initializes the PB7/SCK pin as the serial clock input. MSTR can
be set at any time regardless of the state of SPE. Reset clears MSTR.
1 = Master mode selected
0 = Slave mode selected
10.7.2 SIOP Status Register
The read-only SIOP status register (SSR) contains two bits. One bit
indicates that a SIOP transfer is complete, and the other indicates that
an invalid access of the SIOP data register occurred while a transfer was
in progress.
$000B Bit 7
6
5
4
3
2
1
Bit 0
Read: SPIF DCOL
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 10-7. SIOP Status Register (SSR)
SPIF — Serial Peripheral Interface Flag
This clearable, read-only bit is set automatically on the eighth rising
edge on the PB7/SCK pin and indicates that a data transmission took
place. SPIF does not inhibit further transmissions. Clear SPIF by
reading the SIOP status register while SPIF is set and then reading or
writing the SIOP data register. Reset clears SPIF.
1 = Transmission complete
0 = Transmission not complete
DCOL — Data Collision Flag
Technical Data
126
Serial Input/Output Port (SIOP)
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MC68HC705P9 — Rev. 4.0
MOTOROLA