MC68HC705P9 Datasheet, PDF (49/160 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Instruction Set
I — Interrupt Mask
Setting the interrupt mask disables interrupts. If an interrupt request
occurs while the interrupt mask is logic zero, the CPU saves the CPU
registers on the stack, sets the interrupt mask, and then fetches the
interrupt vector. If an interrupt request occurs while the interrupt mask
is set, the interrupt request is latched. Normally, the CPU processes
the latched interrupt as soon as the interrupt mask is cleared again.
A return from interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After any
reset, the interrupt mask is set and can be cleared only by a software
instruction.
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logical
operation, or data manipulation produces a negative result.
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logical
operation, or data manipulation produces a result of $00.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow flag.
4.7 Instruction Set
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
MC68HC705P9 — Rev. 4.0
MOTOROLA
Central Processor Unit (CPU)
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Technical Data
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