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PXS30 Datasheet, PDF (83/139 Pages) Freescale Semiconductor, Inc – PXS30 Microcontroller
Electrical characteristics
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances
CF, CP1, and CP2 are initially charged at the source voltage VA (please see the equivalent circuit in
Figure 10): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch is
closed).
VCS
VA
VA2
1
VA1
Voltage Transient on CS
2
V <0.5 LSB
1 < (RSW + RAD) CS << TS
2 = RL (CS + CP1 + CP2)
TS t
Figure 11. Transient behavior during sampling phase
In particular two different transient periods can be distinguished:
• A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling
capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case
(since the time constant in reality would be faster) in which CP2 is reported in parallel to CP1 (call
CP = CP1 + CP2), the two capacitances CP and CS are in series, and the time constant is:
1
=
RSW
+
RAD

-C----P---------C----S--
CP + CS
Eqn. 12
Equation 12 can again be simplified considering only CS as an additional worst condition. In
reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in
the very worst case: the sampling time TS is always much longer than the internal time constant:
1  RSW + RAD  CS « TS
Eqn. 13
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1
on the capacitance according to Equation 14:
VA1  CS + CP1 + CP2 = VA  CP1 + CP2
Eqn. 14
• A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance)
through the resistance RL: again considering the worst case in which CP2 and CS were in parallel
to CP1 (since the time constant in reality would be faster), the time constant is:
2  RL  CS + CP1 + CP2
Eqn. 15
In this case, the time constant depends on the external circuit: in particular imposing that the
transient is completed well before the end of sampling time TS, a constraints on RL sizing is
obtained:
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
83