PXS30 Datasheet, PDF (105/139 Pages) Freescale Semiconductor, Inc – PXS30 Microcontroller

Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE1,2
Flash
Init
PHASE3
Device
Config
DRUN
Application
Execution
Electrical characteristics
T_{FRL, min} < T_RESET < T_{FRL, max}
Figure 24. Functional reset sequence long
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE3
DRUN
Application
Execution
T_{FRS, min} < T_RESET < T_{FRS, max}
Figure 25. Functional reset sequence short
The reset sequences shown in Figure 24 and Figure 25 are triggered by functional reset events. RESET is
driven low during these two reset sequences only if the corresponding functional reset source (which
triggered the reset sequence) was enabled to drive RESET low for the duration of the internal reset
sequence. See the RGM_FBRE register in the PXS30 Reference Manual (PXS30RM) for more
information.
3.21.3 Reset sequence trigger mapping
The following table shows the possible trigger events for the different reset sequences, depending on the
VREG mode (external or internal). It specifies the reset sequence start conditions as well as the reset
sequence end indications that are the basis for the timing data provided in Table 58.
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
105