PXS30 Datasheet, PDF (103/139 Pages) Freescale Semiconductor, Inc – PXS30 Microcontroller

Electrical characteristics
3.21.1 Reset sequence duration
Table 58 specifies the minimum and the maximum reset sequence duration for the five different reset
sequences described in Section 3.21.2, Reset sequence description.”
Table 58. RESET sequences
No. Symbol
Parameter
T_Reset
Unit
Min Typ Max¹
1 T_DRB CC
Destructive Reset Sequence, BIST enabled
60
65
70
ms
2 T_DR
CC
Destructive Reset Sequence, BIST disabled
40 400 1000 µs
3 T_ERLB CC
External Reset Sequence Long, BIST enabled
60
65
70
ms
4 T_FRL CC
Functional Reset Sequence Long
40 300 600 µs
5 T_FRS CC
Functional Reset Sequence Short
1
3
10 µs
NOTES:
1 _{The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of}
RESET by an external reset generator.
3.21.2 Reset sequence description
The figures in this section show the internal states of the PXS30 during the five different reset sequences.
The doted lines in the figures indicate the starting point and the end point for which the duration is
specified in Table 58. The start point and end point conditions as well as the reset trigger mapping to the
different reset sequences is specified in Section 3.21.3, Reset sequence trigger mapping.”
With the beginning of DRUN mode, the first instruction is fetched and executed. At this point, application
execution starts and the internal reset sequence is finished.
The following figures show the internal states of the PXS30 during the execution of the reset sequence and
the possible states of the RESET signal pin.
NOTE
RESET is a bidirectional pin. The voltage level on this pin can either be
driven low by an external reset generator or by the PXS30 internal reset
circuitry. A high level on this pin can only be generated by an external pull
up resistor which is strong enough to overdrive the weak internal pull down
resistor. The rising edge on RESET in the following figures indicates the
time when the device stops driving it low. The reset sequence durations
given in Table 58 are applicable only if the internal reset sequence is not
prolonged by an external reset generator keeping RESET asserted low
beyond the last PHASE3.
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
103