PXS30 Datasheet, PDF (4/139 Pages) Freescale Semiconductor, Inc – PXS30 Microcontroller

Introduction
Table 1. PXS30 Family Feature Set (continued)
Features
PXS3010
PXS3015
PXS3020
Clocking
Clock monitor unit
(CMU)
3 modules
Clock output
2 modules
Frequency-modulated
phase-locked loop
(FMPLL)
2 modules (system and auxiliary)
IRCOSC – 16 MHz
1
XOSC 4 MHz – 40 MHz
1
Supply
Power management unit
Yes
(PMU)
1.2 V low-voltage
1
detector (LVD12)
1.2 V high-voltage
1
detector (HVD12)
2.7 V low-voltage
4
detector (LVD27)
Debug
Nexus
Class 3+ (for cores and SRAM ports)
Packages MAPBGA
257 pins
473 pins
473 pins
Temperature Ambient
See the T_A recommended operating condition in the device data sheet
NOTES:
1 _{Sphere of Replication.}
2 _{Does not include Test or Shadow Flash memory space.}
3 _{Available only on 473-pin package.}
4 _{DDR available only on 473 package. Other modules available as follows:}
EBI or DDR on 473 package.
EBI + PDI on 473 package.
DDR + PDI on 473 package
PDI only on 257 package.
1.3 Block diagram
Figure 1 shows a top-level block diagram of the PXS30 device.
PXS30 Microcontroller Data Sheet, Rev. 1
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor