PXS30 Datasheet, PDF (80/139 Pages) Freescale Semiconductor, Inc – PXS30 Microcontroller

Electrical characteristics
Table 22. FMPLL electrical characteristics (continued)
Symbol
Parameter
Conditions
Min Typ Max Unit
t_LOCK P Lock time
t_lpll
D FMPLL lock time ^{5, 6}
Stable oscillator (f_PLLIN = 4 MHz), —
stable V_DD
—
—
— 200 µs
— TBD s
t_dc
D Duty cycle of reference
C_JITTER T CLKOUT period jitter^7,8,9,10
—
40
—
60 %
Peak-to-peak (clock edge to clock TBD — TBD ps
edge), f_SYS maximum
t_PKJIT
Long-term jitter (avg. over 2 ms
interval), f_SYS maximum
T Single period jitter (peak to peak) PHI @ 16 MHz,
Input clock @ 4 MHz
TBD — TBD ns
—
— ±500 ps
t_LTJIT T Long term jitter
PHI @ 16 MHz,
Input clock @ 4 MHz
—
—
±6 ns
f_LCK D Frequency LOCK range
—
TBD — TBD %
f_sys
f_UL
D Frequency un-LOCK range
—
TBD — TBD %
f_sys
f_CS D Modulation Depth
f_DS
Center spread
Down Spread
TBD — TBD %
TBD
—
TBD ^fsys
f_MOD D Modulation frequency¹¹
—
TBD — TBD kHz
NOTES:
1 _{Considering operation with FMPLL not bypassed.}
2 _{“Loss of Reference Frequency” window is the reference frequency range outside of which the FMPLL is in self}
clocked mode.
3 _{Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls}
outside the f_LOR window.
4 _{fVCO is the frequency at the output of the VCO; its range is 256–512 MHz.}
f_SCM is the self-clocked mode frequency (free running frequency); its range is 20–150 MHz.
f_SYS = f_VCOODF
5 _{This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for}
this FMPLL, load capacitors should not exceed these limits.
6 _{This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control}
bits in the synthesizer control register (SYNCR).
7 _{This value is determined by the crystal manufacturer and board design.}
8 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum}
f_SYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the FMPLL circuitry via V_DDPLL and V_SSPLL and variation in crystal oscillator frequency
increase the C_JITTER percentage for a given interval.
9 _{Proper PC board layout procedures must be followed to achieve specifications.}
10 _{Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and}
either f_CS or f_DS (depending on whether center spread or down spread modulation is enabled).
11 _{Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 kHz.}
PXS30 Microcontroller Data Sheet, Rev. 1
80
Preliminary—Subject to Change Without Notice
Freescale Semiconductor