PXS30 Datasheet, PDF (106/139 Pages) Freescale Semiconductor, Inc – PXS30 Microcontroller

Electrical characteristics
Table 59. Reset sequence trigger—reset sequence
Reset Sequence
Reset
Sequence
Trigger
Reset
Sequence
Start
Condition
Reset
Sequence
End
Indication
Destructive
Reset
Sequence,
BIST
enabled²
Destructive
Reset
Sequence,
BIST
disabled²
External
Reset
Sequence
Long,
BIST
enabled
Functional
Reset
Sequence
Long
Functional
Reset
Sequence
Short
All active
I
internal
destructive
reset sources
(LVDs or
internal HVD
during
E
power-up and
during
operation)
Assertion of
RESET_SUP⁴
Assertion of I/E
RESET⁵
Section 3.
21.4.1,
Internal
VREG
mode”
Section 3.
21.4.2,
External
VREG
mode”
Section 3.
21.4.3,
external
Reset via
RESET”
Release of
RESET³
triggers
cannot trigger
cannot
trigger
cannot
trigger
cannot
trigger
cannot
trigger
cannot
trigger
cannot
trigger
triggers⁶ triggers⁷ triggers⁸
All internal
I/E
functional
reset sources
configured
for long reset
Sequence
starts with
internal
reset
trigger
Release of
RESET⁹
cannot trigger
cannot
trigger
triggers
cannot
trigger
All internal
I/E
functional
reset sources
configured
for short
reset
cannot trigger
cannot
trigger
cannot
trigger
triggers
NOTES:
1 _{VREG Mode: I = Internal VREG Mode, E = External VREG Mode.}
2 _{Whether BIST is executed or not depends on device configuration data stored in the shadow sector of the NVM.}
3 _{End of the internal reset sequence (as specified in Table 58) can only be observed by release of RESET if it is not held low}
externally beyond the end of the internal sequence which would prolong the internal reset PHASE3 until RESET is released
externally.
4 _{In external VREG mode only.}
5 _{The assertion of RESET can only trigger a reset sequence if the device was running (RESET released) before.}
RESET does not gate a Destructive Reset Sequence, BIST enabled or a Destructive Reset Sequence, BIST
disabled. However, it can prolong these sequences if RESET is held low externally beyond the end of the internal
sequence (beyond PHASE3).
6 _{If RESET is configured for long reset (default) and if BIST is enabled via device configuration data stored in the}
shadow sector of the NVM.
PXS30 Microcontroller Data Sheet, Rev. 1
106
Preliminary—Subject to Change Without Notice
Freescale Semiconductor