PXS30 Datasheet, PDF (125/139 Pages) Freescale Semiconductor, Inc – PXS30 Microcontroller

3.22.8.3 MII async inputs signal timing (CRS and COL)
Table 71. MII async inputs signal timing¹
No.
Parameter
9 CRS, COL minimum pulse width
NOTES:
1 _{Output pads configured with SRC = 0b11.}
Min
Max
1.5
—
Electrical characteristics
Unit
TX_CLK period
CRS, COL
9
Figure 53. MII async inputs timing diagram
3.22.8.4 MII serial management channel timing (MDIO and MDC)
The FEC functions correctly with a maximum MDC frequency of 5 MHz.
Table 72. MII serial management channel timing¹
No.
Parameter
10 MDC falling edge to MDIO output invalid (minimum propagation delay)
11 MDC falling edge to MDIO output valid (max prop delay)
12 MDIO (input) to MDC rising edge setup
13 MDIO (input) to MDC rising edge hold
14 MDC pulse width high
15 MDC pulse width low
NOTES:
1 _{Output pads configured with SRC = 0b11.}
Min
0
—
10
0
40%
40%
Max
—
25
—
—
60%
60%
Unit
ns
ns
ns
ns
MDC period
MDC period
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
125