PXS30 Datasheet, PDF (112/139 Pages) Freescale Semiconductor, Inc – PXS30 Microcontroller

Electrical characteristics
MCK
Command
Address
Read
t_OS
t_OH
DQS (in)
t_{DQSEN (min)}
t_DQSEN
Figure 33. DDR read timing, DQSEN
Figure 34 provides the AC test load for the DDR bus.
Output
Z₀ = 50 
R_L = 50 
V_{DD_MEM_IO}/2
Figure 34. DDR AC test load
3.22.2 IEEE 1149.1 (JTAG) interface timing
Table 62. JTAG pin AC electrical characteristics
No. Symbol
Parameter
1
t_JCYC
D TCK cycle time ¹
2
t_JDC
D TCK clock pulse width (measured at V_DDE/2)
3 t_TCKRISE D TCK rise and fall times (40%–70%)
4 t_TMSS, t_TDIS D TMS, TDI data setup time
5 t_TMSH, t_TDIH D TMS, TDI data hold time
6 t_TDOV D TCK low to TDO data valid
7
t_TDOI
D TCK low to TDO data invalid
8 t_TDOHZ D TCK low to TDO high impedance
11 t_BSDV D TCK falling edge to output valid
12 t_BSDVZ D TCK falling edge to output valid out of high impedance
13 t_BSDHZ D TCK falling edge to output high impedance
14 t_BSDST D Boundary scan input valid to TCK rising edge
15 t_BSDHT D TCK rising edge to boundary scan input invalid
Conditions
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—
—
—
—
—
—
—
—
—
—
—
—
Min Max Unit
100 — ns
40 60 ns
— 3 ns
5 — ns
25 — ns
— 20 ns
0 — ns
— 20 ns
— 50 ns
— 50 ns
— 50 ns
50 — ns
50 — ns
PXS30 Microcontroller Data Sheet, Rev. 1
112
Preliminary—Subject to Change Without Notice
Freescale Semiconductor