PXS30 Datasheet, PDF (130/139 Pages) Freescale Semiconductor, Inc – PXS30 Microcontroller

Electrical characteristics
3.22.10 I²C Timing
Table 74. I²C SCL and SDA input timing specifications
No. Symbol
Parameter
Value
Unit
Min Max
1
— D Start condition hold time
2
— D Clock low time
2 — IP bus cycle¹
8 — IP bus cycle¹
4
— D Data hold time
6
— D Clock high time
0.0 —
ns
4 — IP bus cycle¹
7
— D Data setup time
8
— D Start condition setup time (for repeated start condition only)
9
— D Stop condition setup time
0.0 —
ns
2 — IP bus cycle¹
2 — IP bus cycle¹
NOTES:
1 _{Inter Peripheral Clock is the clock at which the I}2_{C peripheral is working in the device.}
Table 75. I²C SCL and SDA output timing specifications
No. Symbol
Parameter
Value
Unit
Min Max
1¹
— D Start condition hold time
2¹
— D Clock low time
3³
— D SCL/SDA rise time
4¹
— D Data hold time
5¹
— D SCL/SDA fall time
6¹
— D Clock high time
7¹
— D Data setup time
8¹
— D Start condition setup time (for repeated start condition only)
9¹
— D Stop condition setup time
6 — IP bus cycle²
10 — IP bus cycle¹
— 99.6
ns
7 — IP bus cycle¹
— 99.5
ns
10 — IP bus cycle¹
2 — IP bus cycle¹
20 — IP bus cycle¹
10 — IP bus cycle¹
NOTES:
1 _{Programming IBFD (I}2_{C bus Frequency Divider) with the maximum frequency results in the minimum output timings}
listed. The I²C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.
The actual position is affected by the prescale and division values programmed in IFDR.
2 _{Inter Peripheral Clock is the clock at which the I}2_{C peripheral is working in the device.}
3 _{Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL}
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
PXS30 Microcontroller Data Sheet, Rev. 1
130
Preliminary—Subject to Change Without Notice
Freescale Semiconductor