PXS30 Datasheet, PDF (19/139 Pages) Freescale Semiconductor, Inc – PXS30 Microcontroller

Package pinouts and signal descriptions
2 Package pinouts and signal descriptions
2.1 Package pinouts
Figure 2 shows the PXS30 in the 257 MAPBGA package. Figure 3 through Figure 6 show the PXS30 in
the 473 MAPBGA package.
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
A VSS_
HV_IO
VSS_
HV_IO
VDD_
HV_IO
nexus
MDO[5]
nexus
MDO[7]
nexus
MDO[9]
flexray
CB_TX
flexray
CA_TR_
EN
VDD_
HV_IO
fec
RXD[2]
fec
RX_
CLK
fec
fec
fec
fec VSS_ VSS_ A
RXD[0] MDIO TX_EN TXD[3] HV_IO HV_IO
B VSS_ VSS_ mc_cgl
HV_IO HV_IO clk_out
can1
TXD
nexus
MDO
[14]
dspi2
CS1
flexray
CB_TR_
EN
flexray
CA_TX
VSS_
HV_IO
fec
RXD[3]
fec
RX_ER
fec
RXD[1]
fec
TX_ER
fec
TX_
CLK
can0 VDD_ VSS_ B
TXD HV_IO HV_IO
C VDD_
HV_IO
nexus
MDO
[15]
VSS_
HV_IO
FCCU_
F[1]
flexray
CB_RX
etimer0
ETC[0]
etimer0
ETC[1]
etimer0
ETC[2]
etimer0
ETC[3]
JCOMP
fec
CRS
fec
TXD[0]
fec
COL
can0
RXD
VSS_
HV_PDI
pdi
DATA
[5]
pdi C
CLOCK
D
nexus
MDO
[2]
nexus
MDO
[3]
can1
RXD
dspi0 RESERV etimer0 etimer0 VDD_ VSS_ fec
fec
fec
SOUT ED ETC[5] ETC[4] HV_FLA HV_FLA TXD[2] TXD[1] RX_DV
fec
MDC
VDD_ VSS_
HV_PDI HV_IO
pdi
DATA
[0]
pdi
DATA
D
[1]
E
nexus
MDO
[0]
nexus
MDO
[1]
flexray
CA_RX
NMI
pdi
LINE_V
pdi
DATA
[2]
pdi
DATA
[3]
pdi
DATA
E
[4]
F nexus
MDO[6]
nexus
MDO
[11]
dspi1
SOUT
dspi1
SIN
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
mc_cgl
clk_out
pdi
DATA
[6]
pdi
DATA
[7]
pdi
DATA
F
[8]
G
nexus
MDO
[4]
VDD_
HV_IO
dspi0
SCK
dspi1
SCK
VDD_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VDD_
LV_
COR
pdi
DATA
pdi
DATA
pdi
DATA
pdi
FRAME_
G
[9]
[10] [11]
V
H
nexus
MDO
[10]
VSS_
HV_IO
dspi0
CS0
dspi1
CS0
VDD_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VDD_
LV_
COR
pdi
DATA
pdi
DATA
VDD_
HV_
flexpwm
0
H
[12] [13] PDI X[0]
J nexus nexus dspi2 dspi2
MCKO MDO[8] CS0 CS2
VDD_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VDD_
LV_
COR
pdi
DATA
pdi
DATA
VSS_
HV_
flexpwm
0
J
[14] [15] PDI X[1]
K
nexus
MSEO_
B[0]
nexus
MSEO_
B[1]
nexus
RDY_B
dspi0
SIN
VDD_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VDD_
LV_
COR
flexpwm
0
flexpwm
0
flexpwm
0
flexpwm
0
K
X[2] X[3] A[1] B[0]
L nexus nexus dspi2
EVTO_B EVTI_B SCK
nexus
MDO
[13]
VDD_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VSS_
LV_
COR
VDD_
LV_
COR
VDD_HV
_DRAM_
TCK
flexpwm
0
TDO
L
VREF
B[1]
M
VDD_
HV_
OSC
VDD_
HV_IO
dspi1
CS2
nexus
MDO
[12]
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
VDD_
LV_
COR
flexpwm
0
TDI
B[2]
TMS
flexpwm
1
M
A[1]
N _XTALIN
VSS_
HV_IO
dspi0
CS3
VSS_
LV_PLL
flexpwm
0
flexpwm
0
flexpwm
1
flexpwm
1
N
B[3] A[2] A[0] B[0]
P
VSS_
HV_
OSC
RESET
dspi0
CS2
VDD_ etimer1 etimer1
LV_PLL ETC[1] ETC[2]
adc0
AN[0]
etimer1 VSS_
ETC[3] HV_IO
VDD_
HV_IO
adc0_
adc1
AN[14]
etimer1
ETC[4]
etimer1
ETC[5]
VDD_
HV_IO
flexpwm
0
flexpwm
0
flexpwm
1
P
A[3] A[0] B[1]
R XTAL FCCU_ VSS_HV dspi1
OUT F[0] _IO CS3
adc2
AN[0]
adc2
AN[3]
VDD_ adc2_ VDD_
HV_ adc3 HV_
ADR_13 AN[14] ADR_02
adc0
AN[2]
adc0_
adc1
AN[13]
adc1 VREG_C lin0
AN[1] TRL TXD
VSS_
HV_IO
flexpwm
1
flexpwm
1
R
A[2] B[2]
T VSS_ VDD_ dspi2 adc3
HV_IO HV_IO SOUT AN[0]
adc3
AN[3]
adc2
AN[2]
VSS_ adc2_ VSS_
HV_ adc3 HV_
ADR_13 AN[13] ADR_02
adc0
AN[1]
adc0_
adc1
AN[12]
adc1
AN[0]
adc1
AN[2]
lin0 etimer1 VDD_ VSS_ T
RXD ETC[0] HV_IO HV_IO
U VSS_ VSS_
HV_IO HV_IO
dspi2
SIN
adc3
AN[1]
adc3
AN[2]
adc2
AN[1]
adc2_ adc2_
adc3 adc3
AN[11] AN[12]
VDD_
HV_
ADV
VSS_
HV_
ADV
adc0_
adc1
AN[11]
VREG_
INT_EN
ABLE
RESET_ VDD_HV
SUP _PMU
VSS_
HV_
PMU
VSS_
HV_IO
VSS_ U
HV_IO
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
Figure 2. PXS30 257 MAPBGA pinout (top view)
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
19