PXS30 Datasheet, PDF (20/139 Pages) Freescale Semiconductor, Inc – PXS30 Microcontroller

Package pinouts and signal descriptions
1
2
3
4
5
6
7
8
9
10
11
12
VSS_
A _{HV_IO}
B
VSS_
HV_IO
VDD_
C _{HV_IO}
D
nexus
MDO[1]
nexus
E _MDO[0]
nexus
F _MDO[10]
G
nexus
MCKO
nexus
H _{EVTO_B}
J
nexus
RDY_B
dspi0
K
SCK
dspi0
L
CS0
M
flexpwm0
X[0]
VSS_
HV_IO
VDD_
HV_IO
nexus
MDO[5]
nexus
MDO[7]
nexus
MDO[9]
flexray
flexray
fec
CB_TX CA_TR_EN RX_DV
VSS_
HV_IO
mc_cgl
clk_out
can1
nexus
dspi2
flexray
flexray
fec
TXD MDO[14] CS1 CB_TR_EN CA_TX RXD[3]
nexus
MDO[15]
VSS_
HV_IO
FCCU_
F[1]
flexray
CB_RX
etimer0
ETC[4]
etimer0
ETC[1]
etimer0
ETC[2]
etimer0
ETC[3]
nexus
can1
MDO[3]
RXD
dspi0
SOUT
RESERVED
etimer0
ETC[5]
etimer0
ETC[0]
VDD_
HV_IO
VSS_
HV_IO
nexus
MDO[2]
flexray
CA_RX
NMI
nexus
nexus
MDO[11] MDO[6]
nexus
MDO[4]
VDD_
VDD_
VDD_
VDD_
LV_COR LV_COR LV_COR LV_COR
VDD_
HV_IO
nexus
nexus
MDO[8] MSEO_B[1]
VDD_
VSS_
VSS_
VSS_
LV_COR LV_COR LV_COR LV_COR
VSS_
nexus
nexus
HV_IO MSEO_B[0] EVTI_B
VDD_
VSS_
VSS_
VSS_
LV_COR LV_COR LV_COR LV_COR
nexus
nexus
dspi1
MDO[13] MDO[12]
SIN
VDD_
VSS_
VSS_
VSS_
LV_COR LV_COR LV_COR LV_COR
dspi1
dspi1
dspi1
CS0
SCK
SOUT
VDD_
VSS_
VSS_
VSS_
LV_COR LV_COR LV_COR LV_COR
dspi2
dspi2
VSS_
CS2
CS0
HV_IO
VDD_
VSS_
VSS_
VSS_
LV_COR LV_COR LV_COR LV_COR
VDD_
dspi0
VDD_
HV_IO
SIN
HV_IO
VDD_
VSS_
VSS_
VSS_
LV_COR LV_COR LV_COR LV_COR
fec
MDIO
fec
RX_ER
fec
TXD[2]
JCOMP
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
fec
TX_CLK
fec
TXD[0]
fec
TXD[1]
VSS_
HV_IO
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
fec
TX_EN
fec
RXD[0]
fec
CRS
VSS_
HV_FLA
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
Figure 3. PXS30 473 MAPBGA pinout (northwest, viewed from above)
flexpwm0
N
A[0]
flexpwm0
P
B[0]
flexpwm0
R
X[2]
flexpwm0
T
B[3]
U
flexpwm1
B[0]
V
VDD_
HV_OSC
W XTALIN
Y
VSS_
HV_OSC
AA XTALOUT
AB
VSS_
HV_IO
VSS_
AC _{HV_IO}
VSS_
HV_IO
flexpwm0
B[1]
flexpwm0
X[3]
flexpwm1
A[0]
flexpwm1
B[1]
VDD_
HV_IO
VSS_
HV_IO
RESET
FCCU_
F[0]
VDD_
HV_IO
VSS_
HV_IO
flexpwm0
X[1]
flexpwm0
A[2]
flexpwm0
A[1]
flexpwm1
A[1]
flexpwm1
A[2]
flexpwm1
B[2]
dspi0
CS3
dspi0
CS2
VSS_
HV_IO
dspi2
SOUT
dspi2
SIN
1
2
3
flexpwm0
B[2]
flexpwm0
A[3]
VSS_
HV_IO
VDD_
HV_IO
dspi2
SCK
dspi1
CS2
VSS_
LV_PLL
VDD_
LV_PLL
dspi1
CS3
flexpwm1
X[2]
flexpwm1
A[3]
flexpwm1
X[0]
flexpwm1
X[1]
flexpwm1
X[3]
flexpwm1
B[3]
4
5
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
adc3
AN[0]
adc3
AN[1]
adc3
AN[2]
adc3
AN[3]
6
adc2_adc3 adc2_adc3
AN[11] AN[14]
adc2_adc3 adc2
AN[12]
AN[0]
adc2_adc3 adc2
AN[13]
AN[1]
VDD_HV_ VSS_HV_
ADR_23 ADR_23
etimer1
ETC[1]
VDD_
HV_ADV
adc2
AN[2]
adc2
AN[3]
7
8
9
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
etimer1
ETC[2]
VSS_
HV_ADV
adc0
AN[0]
adc0
AN[1]
10
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VSS_
LV_COR
VDD_
LV_COR
etimer1
ETC[3]
adc0
AN[2]
adc0
AN[4]
adc0
AN[3]
VSS_
HV_IO
adc0
AN[5]
adc0
AN[6]
VDD_
HV_ADR_0
11
12
Figure 4. PXS30 473 MAPBGA pinout (southwest, viewed from above)
PXS30 Microcontroller Data Sheet, Rev. 1
20
Preliminary—Subject to Change Without Notice
Freescale Semiconductor