PXS30 Datasheet, PDF (108/139 Pages) Freescale Semiconductor, Inc – PXS30 Microcontroller

Electrical characteristics
V
VDD_HV_PMU
VDD_HV_IO
VDD_HV_FLASH
VDD_HV_ADV
t
V
0.8 × VDD_HV_IO
RESET_SUP
0.2 × VDD_HV_IO
T_{Reset, max} starts here _t
T_{Reset, min} starts here
Figure 27. External VREG mode, RESET_SUP rises after V_{DD_HV_xxx} are stable
V
LvdReg + 3.5%
LvdReg – 3.5%
VDD_HV_PMU
VDD_HV_IO
VDD_HV_FLASH
VDD_HV_ADV
t
V
RESET_SUP
T_{Reset, max} starts here
t
T_{Reset, min} starts here
Figure 28. External VREG mode, RESET_SUP rises with V_{DD_HV_xxx}
NOTE
In case RESET_SUP has reached a valid high level before V_{DD_HV_IO} is
stable, the reset sequence will start as documented in Figure 28 as the
RESET_SUP input circuitry needs a valid V_{DD_HV_IO} rail in order to detect
a high level on RESET_SUP.
PXS30 Microcontroller Data Sheet, Rev. 1
108
Preliminary—Subject to Change Without Notice
Freescale Semiconductor