PXS30 Datasheet, PDF (102/139 Pages) Freescale Semiconductor, Inc – PXS30 Microcontroller

Electrical characteristics
Table 56. DRAM pads AC electrical specifications (V_{DD_HV_DRAM} (continued) = 1.8 V)
No.
Pad Name
Prop. Delay (ns)
L  H/H  L¹
Min
Max
Rise/Fall Edge
(ns)
Min
Max
Drive Load
(pF)
Drive/Slew
Rate Select
MSB, LSB
2
DRAM DQ
1.4/1.4
2.4/2.4
0.6/1.0
2.7/2.6
5
000
1.7/1.7
2.8/2.7
0.2/0.4
0.5/0.6
20
1.4/1.5
2.4/2.5
1.1/1.1
3.0/2.7
5
001
1.7/1.7
2.8/2.8
0.4/0.4
0.7/0.7
20
1.4/1.5
2.4/2.4
1.0/1.1
2.9/2.7
5
010
1.7/1.7
2.8/2.7
0.3/0.4
0.6/0.7
20
1.4/1.5
2.5/2.5
1.5/1.1
3.1/2.6
5
110
1.7/1.8
2.8/2.8
0.4/0.4
0.7/0.6
20
3
DRAM CLK
1.4/1.4
2.4/2.4
0.4/0.6
2.7/2.7
5
000
1.6/1.6
2.7/2.7
0.7/0.9
1.8/3.4
20
1.4/1.4
2.4/2.4
1.1/1.1
3.0/2.8
5
001
1.7/1.7
2.7/2.7
0.3/0.4
1.0/1.1
20
1.4/1.4
2.4/2.4
0.9/1.1
3.0/2.8
5
010
1.6/1.6
2.7/2.7
0.3/0.4
0.9/1.0
20
1.4/1.4
2.5/2.5
1.5/1.2
3.2/2.6
5
110
1.7/1.7
2.7/2.7
0.4/0.4
1.1/1.2
20
NOTES:
1 _{L  H signifies low-to-high propagation delay and H  L signifies high-to-low propagation delay.}
3.20 RESET characteristics
3.20.1 RESET pin characteristics
Table 57. RESET pin characteristics
No. Symbol
Parameter
1 W_FRST SR RESET pulse is sure to be filtered
2 W_NFRST SR RESET pulse is sure not to be filtered
Conditions
—
—
Min Max Unit
— 70 ns
400 — ns
3.21 Reset sequence
This section shows the duration for different reset sequences. It describes the different reset sequences and
it specifies the start conditions and the end indication for the reset sequences depending on internal or
external VREG mode.
PXS30 Microcontroller Data Sheet, Rev. 1
102
Preliminary—Subject to Change Without Notice
Freescale Semiconductor