1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (9/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

1Gb DDR3L – AS4C64M16D3L
Functional Description
The DDR3L SDRAM is a high-speed dynamic random access memory internally configured as an eight-bank DRAM.
The DDR3L SDRAM uses an 8n prefetch architecture to achieve high speed operation. The 8n Prefetch architecture
is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or
write operation for the DDR3L SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM
core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write operation to the DDR3L SDRAM are burst oriented, start at a selected location, and continue for a
burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration
of an Active command, which is then followed by a Read or Write command. The address bits registered coincident
with the Active command are used to select the bank and row to be activated (BA0-BA2 select the bank; A0-A12
select the row). The address bit registered coincident with the Read or Write command are used to select the
starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10),
and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register.
Prior to normal operation, the DDR3L SDRAM must be powered up and initialized in a predefined manner. The
following sections provide detailed information covering device reset and initialization, register definition, command
descriptions and device operation.
 Power-up and Initialization
The Following sequence is required for POWER UP and Initialization
1. Apply power (RESET# is recommended to be maintained below 0.2 x VDD, all other inputs may be undefined).
RESET# needs to be maintained for minimum 200us with stable power. CKE is pulled “Low” anytime before
RESET# being de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDDmin must be
no greater than 200ms; and during the ramp, VDD>VDDQ and (VDD-VDDQ) <0.3 Volts.
- VDD and VDDQ are driven from a single power converter output, AND
- The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD
on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to
0.95V max once power ramp is finished, AND
- Vref tracks VDDQ/2.
OR
- Apply VDD without any slope reversal before or at the same time as VDDQ.
- Apply VDDQ without any slope reversal before or at the same time as VTT & Vref.
- The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD
on one side and must be larger than or equal to VSSQ and VSS on the other side.
2. After RESET# is de-asserted, wait for another 500us until CKE become active. During this time, the DRAM will
start internal state initialization; this will be done independently of external clocks.
3. Clock (CK, CK#) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes
active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be meeting. Also a
NOP or Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the
CKE registered “High” after Reset, CKE needs to be continuously registered “High” until the initialization sequence
is finished, including expiration of tDLLK and tZQinit.
4. The DDR3L DRAM will keep its on-die termination in high impedance state as long as RESET# is asserted.
Further, the DRAM keeps its on-die termination in high impedance state after RESET# deassertion until CKE is
registered HIGH. The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When
CKE is registered HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be
enabled in MR1, the ODT input signal must be statically held LOW. In all cases, the ODT input signal remains
static until the power up initialization sequence is finished, including the expiration of tDLLK and tZQinit.
5. After CKE being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS
command to load mode register.(tXPR=max (tXS, 5tCK))
6. Issue MRS command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low”
to BA0 and BA2, “High” to BA1)
7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low”
to BA2, “High” to BA0 and BA1)
8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue “DLL Enable”
command, provide “Low” to A0, “High” to BA0 and “Low” to BA1 and BA2)
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command
provide “High” to A8 and “Low” to BA0-BA2)
10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQinit completed.
Confidential
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Rev. 2.0
Aug. /2014