1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (4/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

Figure 2. Block Diagram
CK
CK#
CKE
DLL
CLOCK
BUFFER
RESET#
CS#
RAS#
CAS#
WE#
COMMAND
DECODER
A10/AP
A12/BC#
COLUMN
COUNTER
A0
A9
A11
A12
BA0
BA1
BA2
VSSQ
LDQS
LDQS#
UDQS
UDQS#
ADDRESS
BUFFER
REFRESH
COUNTER
RZQ
DATA
STROBE
BUFFER
DQ0
DQ15
Confidential
1Gb DDR3L – AS4C64M16D3L
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
ZQCL
ZQCS
ZQ
CAL
DQ
Buffer
ODT _LDM
UDM
4
8M x 16
CELL ARRAY
(BANK #0)
Column Decoder
8M x 16
CELL ARRAY
(BANK #1)
Column Decoder
8M x 16
CELL ARRAY
(BANK #2)
Column Decoder
8M x 16
CELL ARRAY
(BANK #3)
Column Decoder
8M x 16
CELL ARRAY
(BANK #4)
Column Decoder
8M x 16
CELL ARRAY
(BANK #5)
Column Decoder
8M x 16
CELL ARRAY
(BANK #6)
Column Decoder
8M x 16
CELL ARRAY
(BANK #7)
Column Decoder
Rev. 2.0
Aug. /2014