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| 1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (10/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant | |||
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1Gb DDR3L â AS4C64M16D3L
12. The DDR3L SDRAM is now ready for normal operation.
Figure 4. Reset and Initialization Sequence at Power-on Ramping
CK#
CK
VDD
VDDQ
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
T=200μs
tCKSRX
T=500μs
RESET#
CKE
Tmin=10ns
tIS
tDLLK
COMMAND
tIS
tXPR
tMRD
tMRD
tMRD
tMOD
Note 1
MRS
MRS
MRS
MRS
ZQCL
tZQinit
Note 1
VALID
BA
ODT
RTT
MR2
MR3
MR1
MR0
tIS
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
VALID
tIS
VALID
NOTE 1. From time point "Td" until "Tk " NOP or DES commands must be applied between MRS and ZQCL commands.
TIME BREAK
Don't Care
Confidential
10
Rev. 2.0
Aug. /2014
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