1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (32/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

1Gb DDR3L – AS4C64M16D3L
- MPR Functional Description
•One bit wide logical interface via all DQ pins during READ operation.
•Register Read on x16:
•DQL[0] and DQU[0] drive information from MPR.
•DQL[7:1] and DQU[7:1] either drive the same information as DQL [0], or they drive 0b.
•Addressing during for Multi Purpose Register reads for all MPR agents:
•BA [2:0]: don’t care
•A[1:0]: A[1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed
•A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) For Burst Chop 4 cases, the
burst order is switched on nibble base A [2]=0b, Burst order: 0,1,2,3 *) A[2]=1b, Burst order: 4,5,6,7 *)
•A[9:3]: don’t care
•A10/AP: don’t care
•A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0.
•A11 (if available): don’t care
•Regular interface functionality during register reads:
•Support two Burst Ordering which are switched with A2 and A[1:0]=00b.
•Support of read burst chop (MRS and on-the-fly via A12/BC)
•All other address bits (remaining column address bits including A10, all bank address bits) will be ignored by
the DDR3L SDRAM.
•Regular read latencies and AC timings apply.
•DLL must be locked prior to MPR Reads.
NOTE: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
Table 20. MPR MR3 Register Definition
MR3
A[2]
MR3
A[1:0]
Function
Burst Length
BL8
1b
Read Predefined
00b
Pattern for
System
BC4
Calibration
BC4
BL8
1b
01b
RFU
BC4
BC4
BL8
1b
10b
RFU
BC4
BC4
BL8
1b
11b
RFU
BC4
BC4
Read Address
A[2:0]
Burst Order and Data Pattern
000b
Burst order 0, 1, 2, 3, 4, 5, 6, 7
Pre-defined Data Pattern
[0, 1, 0, 1, 0, 1, 0, 1]
000b
Burst order 0, 1, 2, 3
Pre-defined Data Pattern
[0, 1, 0, 1]
100b
Burst order 4, 5, 6, 7
Pre-defined Data Pattern
[0, 1, 0, 1]
000b
Burst order 0, 1, 2, 3, 4, 5, 6, 7
000b
Burst order 0, 1, 2, 3
100b
Burst order 4, 5, 6, 7
000b
Burst order 0, 1, 2, 3, 4, 5, 6, 7
000b
Burst order 0, 1, 2, 3
100b
Burst order 4, 5, 6, 7
000b
Burst order 0, 1, 2, 3, 4, 5, 6, 7
000b
Burst order 0, 1, 2, 3
100b
Burst order 4, 5, 6, 7
 No Operation (NOP) Command
The No operation (NOP) command is used to instruct the selected DDR3L SDRAM to perform a NOP (CS# low
and RAS#, CAS# and WE# high). This prevents unwanted commands from being registered during idle or wait
states. Operations already in progress are not affected.
 Deselect Command
The Deselect function (CS# HIGH) prevents new commands from being executed by the DDR3L SDRAM. The
DDR3L SDRAM is effectively deselected. Operations already in progress are not affected.
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Rev. 2.0
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