1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (24/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

1Gb DDR3L – AS4C64M16D3L
Table 17. IDD specification parameters and test conditions (V_DD = 1.35V)
Parameter & Test Condition
Symbol
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; BL: 8^*1; AL: 0; CS#: High between ACT and
PRE; Command, Address, Bank Address Inputs: partially toggling; Data IO:
MID-LEVEL; DM:stable at 0; Bank Activity: Cycling with one bank active at a
I_DD0
time: 0,0,1,1,2,2,...;Output Buffer and RTT: Enabled in Mode Registers^*2;
ODT Signal: stable at 0.
-12
Max.
45
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; BL: 8^{*1, 7}; AL:0; CS#: High between ACT, RD
and PRE; Command, Address, Bank Address Inputs, Data IO: partially
toggling; DM:stable at 0; Bank Activity: Cycling with one bank active at a
I_DD1
60
time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers^*2;
ODT Signal: stable at 0.
Precharge Standby Current
CKE: High; External clock: On; BL: 8^*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: partially toggling; Data IO: MID-LEVEL;
I_DD2N
20
DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT:
Enabled in Mode Registers^*2; ODT Signal: stable at 0.
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; BL: 8^*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM:stable
at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
I_DD2P0
10
Mode Registers^*2; ODT Signal: stable at 0; Precharge Power Down Mode:
Slow Exit.^*3
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; BL: 8^*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM:stable
at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
I_DD2P1
12
Mode Registers^*2; ODT Signal: stable at 0; Precharge Power Down Mode:
Fast Exit.^*3
Precharge Quiet Standby Current
CKE: High; External clock: On; BL: 8^*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM:stable I_DD2Q
16
at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers^*2; ODT Signal: stable at 0.
Active Standby Current
CKE: High; External clock: On; BL: 8^*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: partially toggling; Data IO: MID-LEVEL;
I_DD3N
25
DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT:
Enabled in Mode Registers^*2; ODT Signal: stable at 0.
Active Power-Down Current
CKE: Low; External clock: On; BL: 8^*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL;DM:stable I_DD3P
17
at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in
Mode Registers^*2; ODT Signal: stable at 0
Operating Burst Read Current
CKE: High; External clock: On; BL: 8^{*1, 7}; AL: 0; CS#: High between RD;
Command, Address, Bank Address Inputs: partially toggling; DM:stable at
0; Bank Activity: all banks open, RD commands cycling through banks:
I_DD4R
120
0,0,1,1,2,2,...; tput Buffer and RTT: Enabled in Mode Registers^*2; ODT
Signal: stable at 0.
Operating Burst Write Current
CKE: High; External clock: On; BL: 8^*1; AL: 0; CS#: High between WR;
Command, Address, Bank Address Inputs: partially toggling; DM: stable at
0; Bank Activity: all banks open. Output Buffer and RTT: Enabled in Mode
I_DD4W
125
Registers^*2; ODT Signal: stable at HIGH.
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Confidential
24
Rev. 2.0
Aug. /2014