1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (41/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

1Gb DDR3L – AS4C64M16D3L
Figure14. Timing details of Write Leveling sequence
(DQS – DQS# is capturing CK – CK# low at T1 and CK – CK# high at T2)
Notes 5
CK#
T1 t_WLH
tWLS
T2
tWLS t_WLH
CK
Notes 1
Notes 2
COMMAND
MRS
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t_MOD
ODT
Notes 4
Diff_DQS
One Prime DQ:
Notes 3
Prime DQ
t_WLDQSEN
t_WLMRD
Notes 6
t ^{t Notes 6}
DQSL
DQSH
t_WLO
Notes 6
t_DQSL
t ^{Notes 6}
DQSH
t_WLO
t_WLO
Late Remaining DQs
Early Remaining DQs
All DQs are Prime:
Notes 3
Late Prime DQs
Notes 3
Early Prime DQs
t_WLMRD
t_WLO
t_WLOE
t_WLO
t_WLO
t_WLO
t_WLOE
NOTES
t_WLO
t_WLOE
1. MRS: Load MR1 to enter write leveling mode.
2. NOP: NOP or Deselect.
UNDEFINED Driving MODE TIME BREAK Don't Care
3. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the remaining DQs must be driven low, as shown in above Figure,
and maintained at this state through out the leveling procedure.
4. diff_DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. DQS is shown with solid line, DQS# is shown with dotted line.
5. CK, CK# : CK is shown with solid dark line, where as CK# is drawn with dotted line.
6. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is system dependent.
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Rev. 2.0
Aug. /2014