1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (6/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

1Gb DDR3L – AS4C64M16D3L
Ball Descriptions
Table 3. Ball Descriptions
Symbol Type
Description
CK, CK#
Input
Differential Clock: CK and CK# are driven by the system clock. All SDRAM input signals
are sampled on the crossing of positive edge of CK and negative edge of CK#. Output
(Read) data is referenced to the crossings of CK and CK# (both directions of crossing).
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes
LOW synchronously with clock, the internal clock is suspended from the next clock cycle
and the state of output and burst address is frozen as long as the CKE remains LOW.
When all banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes.
BA0-BA2
Input Bank Address: BA0-BA2 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
A0-A12
Input
Address Inputs: A0-A12 are sampled during the BankActivate command (row address
A0-A12) and Read/Write command (column address A0-A9 with A10 defining Auto
Precharge).
A10/AP
Input
Auto-Precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write operation.
(HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH).
A12/BC# Input Burst Chop: A12/BC# is sampled during Read and Write commands to determine if
burst chop (on the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped).
CS#
Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. It is considered part of
the command code.
RAS#
Input
Row Address Strobe: The RAS# signal defines the operation commands in conjunction
with the CAS# and WE# signals and is latched at the crossing of positive edges of CK and
negative edge of CK#. When RAS# and CS# are asserted "LOW" and CAS# is asserted
"HIGH," either the BankActivate command or the Precharge command is selected by the
WE# signal. When the WE# is asserted "HIGH," the BankActivate command is selected
and the bank designated by BA is turned on to the active state. When the WE# is asserted
"LOW," the Precharge command is selected and the bank designated by BA is switched to
the idle state after the precharge operation.
CAS#
Input
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the crossing of positive
edges of CK and negative edge of CK#. When RAS# is held "HIGH" and CS# is asserted
"LOW," the column access is started by asserting CAS# "LOW." Then, the Read or Write
command is selected by asserting WE# “HIGH " or “LOW".
WE#
Input
Write Enable: The WE# signal defines the operation commands in conjunction with the
RAS# and CAS# signals and is latched at the crossing of positive edges of CK and
negative edge of CK#. The WE# input is used to select the BankActivate or Precharge
command and Read or Write command.
LDQS,
LDQS#
UDQS
UDQS#
Input /
Output
Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data Strobe
is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM.
LDQS is for DQ0~7, UDQS is for DQ8~15. The data strobes LDOS and UDQS are paired
with LDQS# and UDQS# to provide differential pair signaling to the system during both
reads and writes.
Confidential
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Rev. 2.0
Aug. /2014