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1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (84/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant
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1Gb DDR3L – AS4C64M16D3L
Figure 70. Dynamic ODT: Behavior with ODT pin being asserted together with write
command for a duration of 6 clock cycles, example for BC4
(via MRS or OTF), AL = 0, CWL = 5.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
COMMAND
ADDRESS
ODT
RTT
DQS, DQS#
DQ
NOP
WRS4
VALID
NOP
NOP
NOP
ODTLcnw
ODTH4
ODTLon
tAON(min)
NOP
ODTLcwn4
tADC(max)
WL
NOP
NOP
NOP
NOP
NOP
NOP
RTT_WR
ODTLoff
tADC(min)
tADC(max)
tAOF(min)
RTT_NOM
tAOF(max)
Din
Din
Din
Din
n
n+1
n+2
n+3
NOTES:
1. ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied. TRANSITIONING DON’T CARE
2. ODT registered low at T5 would also be legal.
TRANSITIONING DATA
Don't Care
Figure 71. Dynamic ODT: Behavior with ODT pin being asserted together with write
command for duration of 4 clock cycles
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
COMMAND
NOP
WRS4
NOP
NOP
NOP
NOP
ADDRESS
VALID
ODTLcnw
ODTH4
ODTLon
ODT
RTT
DQS, DQS#
tAON(min)
ODTLcwn4
tADC(max)
WL
DQ
NOP
NOP
NOP
NOP
ODTLoff
RTT_WR
tAOF(min)
tAOF(max)
Din
Din
Din
Din
n
n+1
n+2
n+3
NOP
NOP
NOTES:
Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. In this example, ODTH4 = 4 is exactly satisfied.
TRANSITIONING DATA
Don't Care
Confidential
84
Rev. 2.0
Aug. /2014
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