1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (28/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

1Gb DDR3L – AS4C64M16D3L
t_WRAPDEN
Timing of WRA command to Power Down entry
(BC4MRS)
WL + 2 +
WR + 1
-
tCK
10
t_REFPDEN Timing of REF command to Power Down entry
1
-
tCK 20, 21
t_MRSPDEN Timing of MRS command to Power Down entry
tMOD(min)
-
ODTLon
ODTLoff
ODTH4
ODT turn on Latency
ODT turn off Latency
ODT high time without write command or
with write command and BC4
WL - 2 = CWL + AL - 2
tCK
WL - 2 = CWL + AL - 2
4
-
tCK
ODTH8
t_AONPD
ODT high time with Write command and BL8
Asynchronous RTT turn-on delay (Power- Down with
DLL frozen)
6
-
tCK
2
8.5
ns
t_AOFPD
Asynchronous RTT turn-off delay (Power-
Down with DLL frozen)
2
8.5
ns
t_AON
RTT turn-on
t_AOF
RTT_Nom and RTT_WR turn-off time
from ODTLoff reference
-225
0.3
225
ps
7
0.7
tCK
8
t_ADC
t_WLMRD
RTT dynamic change skew
First DQS/DQS# rising edge after write
leveling mode is programmed
0.3
0.7
tCK
40
-
tCK
3
t_WLDQSEN
DQS/DQS# delay after write leveling
mode is programmed
25
-
tCK
3
t_WLS
Write leveling setup time from rising CK,
CK# crossing to rising DQS, DQS# crossing
165
-
ps
t_WLH
Write leveling hold time from rising DQS,
DQS# crossing to rising CK, CK# crossing
165
-
ps
t_WLO
Write leveling output delay
0
7.5
ns
t_WLOE
Write leveling output error
0
2
ns
t_RFC
REF command to ACT or REF command time
110
-
ns
t_REFI
Average periodic refresh interval
-40°C to 85°C
-
85°C to 95°C
-
7.8
μs
3.9
μs
NOTE 1: Actual value dependant upon measurement level.
NOTE 2: Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
NOTE 3: The max values are system dependent.
NOTE 4: WR as programmed in mode register.
NOTE 5: Value must be rounded-up to next higher integer value
NOTE 6: There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
NOTE 7: For definition of RTT turn-on time tAON See “Timing Parameters”.
NOTE 8: For definition of RTT turn-off time tAOF See “Timing Parameters”.
NOTE 9: tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
NOTE 10: WR in clock cycles as programmed in MR0.
NOTE 11: The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on
the right side. See “Clock to Data Strobe Relationship”.
NOTE 12: Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter,
this parameter needs to be derated by t.b.d.
NOTE 13: Value is only valid for RON34.
NOTE 14: Single ended signal parameter.
NOTE 15: tREFI depends on TOPER.
NOTE 16: tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK# differential
slew rate. Note for DQ and DM signals, VREF(DC) = VRefDQ(DC). For input only pins except RESET#, VRef(DC)
= VRefCA(DC). See “Address / Command Setup, Hold and Derating”.
NOTE 17: tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS# differential slew
rate. Note for DQ and DM signals, VREF(DC) = VRefDQ(DC). For input only pins except RESET#, VRef(DC) =
VRefCA(DC). See “Data Setup, Hold and Slew Rate Derating”.
NOTE 18: Start of internal write transaction is defined as follows:
- For BL8 (fixed by MRS and on- the-fly): Rising clock edge 4 clock cycles after WL.
- For BC4 (on- the- fly): Rising clock edge 4 clock cycles after WL.
- For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.
NOTE 19: The maximum read preamble is bound by tLZ(DQS)min on the left side and tDQSCK(max) on the right side. See
“Clock to Data Strobe Relationship”.
Confidential
28
Rev. 2.0
Aug. /2014