1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (57/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

1Gb DDR3L – AS4C64M16D3L
- Single-ended requirements for differential signals
Each individual component of a differential signal (CK, CK#, LDQS, UDQS, LDQS#, or UDQS#) has also to comply
with certain requirements for single-ended signals.
CK and CK# have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH(ac) /
VIL(ac)) for ADD/CMD signals) in every half-cycle. LDQS, UDQS, LDQS#, UDQS# have to reach VSEHmin /
VSELmax (approximately the ac-levels (VIH(ac) / VIL(ac)) for DQ signals) in every half-cycle proceeding and
following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if
VIH150(ac)/VIL150(ac) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals
CK and CK#.
Table 29. Single-ended levels for CK, DQSL, DQSU, CK#, DQSL# or DQSU#
Symbol
Parameter
Min.
Max.
Unit Note
VSEH
Single-ended high level for strobes
Single-ended high level for CK, CK#
(V_DD / 2) + 0.175
(V_DD / 2) + 0.175
Note 3
Note 3
V 1,2
V 1,2
VSEL
Single-ended low level for strobes
Single-ended low level for CK, CK#
Note 3
Note 3
(V_DD / 2) - 0.175
(V_DD / 2) - 0.175
V 1,2
V 1,2
NOTE 1: For CK, CK# use VIH/VIL(ac) of ADD/CMD; for strobes (DQSL, DQSL#, DQSU, DQSU#) use VIH/VIL(ac) of DQs.
NOTE 2: VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VIH(ac)/VIL(ac) for ADD/CMD is based on VREFCA; if a reduced
ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
NOTE 3: These values are not defined, however the single-ended signals CK, CK#, DQSL, DQSL#, DQSU, DQSU# need to
be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for
overshoot and undershoot.
- Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each
cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the requirements in the
following table. The differential input cross point voltage Vix is measured from the actual cross point of true and
complete signal to the midlevel between of VDD and VSS.
Table 30. Cross point voltage for differential input signals (CK, DQS)
Symbol
Parameter
Min.
Max.
Unit Note
Differential Input Cross Point Voltage
VIX(CK)
relative to VDD/2 for CK, CK#
- 150
150
mV 2
VIX(DQS) ^{Differential Input Cross Point Voltage}
relative to VDD/2 for DQS, DQS#
- 150
150
mV 2
NOTE 1: Extended range for Vix is only allowed for clock and if single-ended clock input signals CK and CK# is monotonic
with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK -
CK# is larger than 3 V/ns.
NOTE 2: The relation between Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + Vix (Min) - VSEL ≧ 25mV
VSEH - ((VDD/2) + Vix (Max)) ≧ 25mV
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Rev. 2.0
Aug. /2014