1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (33/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

1Gb DDR3L – AS4C64M16D3L
 DLL- Off Mode
DDR3L DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operations
until A0 bit set back to “0”. The MR1 A0 bit for DLL control can be switched either during initialization or later.
The DLL-off Mode operations listed below are an optional feature for DDR3L. The maximum clock frequency for
DLL-off Mode is specified by the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need
to satisfy the refresh interval, tREFI.
Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS Write
Latency (CWL) in MR2 are supported. The DLL-off mode is only required to support setting of both CL=6 and
CWL=6.
DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the data Strobe to
Data relationship (tDQSQ, tQH). Special attention is needed to line up Read data to controller time domain.
Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after the Read
command, the DLL-off mode tDQSCK starts (AL+CL-1) cycles after the read command. Another difference is
that tDQSCK may not be small compared to tCK (it might even be larger than tCK) and the difference between
tDQSCKmin and tDQSCKmax is significantly larger than in DLL-on mode.
The timing relations on DLL-off mode READ operation have shown at the following Timing Diagram (CL=6, BL=8)
Figure 9. DLL-off mode READ Timing Operation
T0
T1
T2
T3
T4
T5
T6
CK#
CK
T7
T8
T9
T10
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ADDRESS
Bank,
Col b
DQS#
(DLL_on)
DQS
RL (DLL_on) = AL + CL = 6 (CL = 6, AL = 0)
CL = 6
DQ (DLL_on)
DQS#
(DLL_off)
DQS
RL (DLL_off) = AL + (CL-1) = 5
Din
Din
Din
Din
Din
Din
Din
Din
b
t_{DQSCK(DLL_off)_min}
b+1
b+2
b+3
b+4
b+5
b+6
b+7
DQ (DLL_off)
DQS#
(DLL_off)
DQS
Din
Din
Din
Din
Din
Din
Din
Din
b
b+1
b+2
b+3
b+4
b+5
b+6
b+7
t_{DQSCK(DLL_off)_max}
DQ (DLL_off)
Din
Din
Din
Din
Din
Din
Din
Din
b
b+1
b+2
b+3
b+4
b+5
b+6
b+7
NOTE 1. The tDQSCK is used here for DQS, DQS# and DQ to have a simplified diagram; the DLL_off shift will affect
both timings in the same way and the skew between all DQ and DQS, DQS# signals will still be tDQSQ.
TRANSITIONING DATA
Don't Care
Confidential
33
Rev. 2.0
Aug. /2014