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| 1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (87/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant | |||
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1Gb DDR3L â AS4C64M16D3L
Figure 76. Transition period for short CKE cycles, entry and exit period overlapping
(AL = 0, WL = 5, tANPD = WL - 1 = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
CK#
CK
COMMAND
REF
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CKE
CKE
tANPD
tANPD
tRFC (min)
PD entry transition period
PD exit transition period
tANPD
short CKE low transition period
short CKE high transition period
tXPDLL
tXPDLL
TIME BREAK
Don't Care
Figure 77. Power-Down Entry, Exit Clarifications-Case 1
T0
T1
T2
Ta0
Ta1
Tb0
Tb1
Tb2
CK#
CK
COMMAND VALID
NOP
NOP
NOP
NOP
NOP
NOP
ADDRESS
CKE
VALID
tPD
tIS
tIH
tCPDED
Enter
Power-Down
Mode
tIH
tIS
tIS
tPD
tCKE
tCPDED
Exit
Power-Down
Mode
Enter
Power-Down
Mode
TIME BREAK
Don't Care
Confidential
87
Rev. 2.0
Aug. /2014
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