1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (48/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

1Gb DDR3L – AS4C64M16D3L
Write Operation
 DDR3L Burst Operation
During a READ or WRITE command, DDR3L will support BC4 and BL8 on the fly using address A12 during the
READ or WRITE (Auto Precharge can be enabled or disabled).
A12=0, BC4 (BC4 = Burst Chop, tCCD=4)
A12=1, BL8
A12 is used only for burst length control, not as a column address.
 WRITE Timing Violations
Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make
sure the DRAM works properly. However, it is desirable for certain minor violations that the DRAM is guaranteed
not to “hang up” and errors be limited to that particular operation.
For the following, it will be assumed that there are no timing violations with regard to the Write command itself
(including ODT, etc.) and that it does satisfy all timing requirements not mentioned below.
 Data Setup and Hold Violations
Should the strobe timing requirements (tDS, tDH) be violated, for any of the strobe edges associated with a write
burst, then wrong data might be written to the memory location addressed with the offending WRITE command.
Subsequent reads from that location might result in unpredictable read data, however, the DRAM will work
properly otherwise.
 Strobe to Strobe and Strobe to Clock Violations
Should the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing
requirements (tDSS, tDSH, tDQSS) be violated, for any of the strobe edges associated with a Write burst, then
wrong data might be written to the memory location addressed with the offending WRITE command. Subsequent
reads from that location might result in unpredictable read data, however the DRAM will work properly otherwise.
 Write Timing Parameters
This drawing is for example only to enumerate the strobe edges that “belong” to a write burst. No actual timing
violations are shown here. For a valid burst all timing parameters for each edge of a burst need to be satisfied (not
only for one edge ).
 Refresh Command
The Refresh command (REF) is used during normal operation of the DDR3L SDRAMs. This command is not
persistent, so it must be issued each time a refresh is required. The DDR3L SDRAM requires Refresh cycles at
an average periodic interval of tREFI. When CS#, RAS#, and CAS# are held Low and WE# High at the rising
edge of the clock, the chip enters a Refresh cycle. All banks of the SDRAM must be precharged and idle for a
minimum of the precharge time tRP(min) before the Refresh Command can be applied. The refresh addressing is
generated by the internal refresh controller. This makes the address bits “Don’t Care” during a Refresh command.
An internal address counter suppliers the address during the refresh cycle. No control of the external address bus
is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in
the precharged (idle) state. A delay between the Refresh Command and the next valid command, except NOP or
DES, must be greater than or equal to the minimum Refresh cycle time tRFC(min).
In general, a Refresh command needs to be issued to the DDR3L SDRAM regularly every tREFI interval. To allow
for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval
is provided. A maximum of 8 Refresh commands can be postponed during operation of the DDR3L SDRAM,
meaning that at no point in time more than a total of 8 Refresh commands are allowed to be postponed. In case
that 8 Refresh commands are postponed in a row, the resulting maximum interval between the surrounding
Refresh commands is limited to 9 x tREFI. A maximum of 8 additional Refresh commands can be issued in
advance (“pulled in”), with each one reducing the number of regular Refresh commands required later by one.
Note that pulling in more than 8 Refresh commands in advance does not further reduce the number of regular
Refresh commands required later, so that the resulting maximum interval between two surrounding Refresh
command is limited to 9 x tREFI. Before entering Self-Refresh Mode, all postponed Refresh commands must be
executed.
Confidential
48
Rev. 2.0
Aug. /2014