1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (56/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

1Gb DDR3L – AS4C64M16D3L
ZQ Calibration Commands
 ZQ Calibration Description
ZQ Calibration command is used to calibrate DRAM Ron and ODT values. DDR3L SDRAM needs longer time to
calibrate output driver and on-die termination circuits at initialization and relatively smaller time to perform
periodic calibrations.
ZQCL command is used to perform the initial calibration during power-up initialization sequence. This command
may be issued at any time by the controller depending on the system environment. ZQCL command triggers the
calibration engine inside the DRAM and once calibration is achieved the calibrated values are transferred from
calibration engine to DRAM IO which gets reflected as updated output driver and on-die termination values.
The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and
the transfer of values. All other ZQCL commands except the first ZQCL command issued after RESET is allowed
a timing period of tZQoper.
ZQCS command is used to perform periodic calibrations to account for voltage and temperature variations. A
shorter timing window is provided to perform the calibration and transfer of values as defined by timing parameter
tZQCS.
No other activities should be performed on the DRAM channel by the controller for the duration of tZQinit,
tZQoper, or tZQCS. The quiet time on the DRAM channel allows calibration of output driver and on-die
termination values. Once DRAM calibration is achieved, the DRAM should disable ZQ current consumption path
to reduce power.
All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller.
ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self refresh. Upon
self-refresh exit, DDR3L
SDRAM will not perform an IO calibration without an explicit ZQ calibration command. The earliest possible time
for ZQ Calibration command (short or long) after self refresh exit is tXS.
In systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper,
tZQinit, or tZQCS between ranks.
Figure 23. ZQ Calibration Timing
CK#
T0
T1
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Tc2
CK
COMMAND
ZQCL
NOP
NOP
NOP
VALID
VALID
ZQCS
NOP
NOP
NOP
VALID
ADDRESS
A10
VALID
VALID
VALID
VALID
CKE
ODT
Notes 1
Notes 2
VALID
VALID
VALID
VALID
Notes 1
Notes 2
DQ Bus
Notes 3
Hi-Z
t_ZQinit or t_ZQoper
ACTIVITIES
Notes 3
NOTES:
1. CKE must be continuously registered high during the calibration procedure.
2. On-die termination must be disabled via the ODT signal or MRS during the calibration procedure.
3. All devices connected to the DQ bus should be high impedance during the calibration procedure.
Hi-Z
t_ZQCS
VALID
VALID
VALID
VALID
ACTIVITIES
TIME BREAK
Don't Care
 ZQ External Resistor Value, Tolerance, and Capacitive loading
In order to use the ZQ calibration function, a 240 ohm +/- 0.1% tolerance external resistor connected between the
ZQ pin and ground. The single resistor can be used for each SDRAM or one resistor can be shared between two
SDRAMs if the ZQ calibration timings for each SDRAM do not overlap. The total capacitive loading on the ZQ pin
must be limited.
Confidential
56
Rev. 2.0
Aug. /2014