1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (69/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

1Gb DDR3L – AS4C64M16D3L
Figure 38. READ to PRECHARGE, RL = 5, AL = 0, CL = 5, tRTP = 4, tRP = 5
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
CK#
CK
COMMAND
NOP
ADDRESS
READ
Bank a,
Col n
NOP
NOP
NOP
tRTP
RL = AL + CL
PRE
Bank a,
(or all)
NOP
NOP
NOP
tRP
NOP
ACT
NOP
Bank a,
Row b
NOP
NOP
DQS, DQS# ^{BL4 Operation:}
T14
T15
NOP
NOP
DQ
BL8 Operation:
DQS, DQS#
DO
DO
DO
DO
n
n+1
n+2
n+3
DQ
DO
DO
DO
DO
DO
DO
DO
DO
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
NOTES:
1. RL = 5 (CL = 5, AL = 0)
2. DOUT n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. The example assumes tRAS.MIN is satisfied at Precharge command time (T5) and that tRC.MIN is satisfied at the next Active command time (T10).
TRANSITIONING DATA
Don't Care
Figure 39. READ to PRECHARGE, RL = 8, AL = CL-2, CL = 5, tRTP = 6, tRP = 5
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
CK#
CK
COMMAND
NOP
ADDRESS
READ
Bank a,
Col n
NOP
NOP
NOP
AL = CL - 2 = 3
NOP
NOP
NOP
tRTP
CL = 5
NOP
NOP
PRE
Bank a,
(or all)
NOP
NOP
NOP
tRP
DQS, DQS# ^{BL4 Operation:}
T14
T15
NOP
ACT
Bank a,
Row b
DQ
BL8 Operation:
DQS, DQS#
DO
DO
DO
DO
n
n+1
n+2
n+3
DQ
DO
DO
DO
DO
DO
DO
DO
DO
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
NOTES:
1. RL = 8 (CL = 5, AL = CL - 2)
2. DOUT n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. The example assumes tRAS.MIN is satisfied at Precharge command time (T10) and that tRC.MIN is satisfied at the next Active command time (T15).
TRANSITIONING DATA
Don't Care
Confidential
69
Rev. 2.0
Aug. /2014