1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (31/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

1Gb DDR3L – AS4C64M16D3L
- Multi-Purpose Register (MPR)
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit
sequence.
Figure 8. MPR Block Diagram
Memory Core
(all banks precharged)
MRS 3
【A2】
Multipurpose register
Pre-defined data for Reads
DQ, DM, DQS, DQS#
To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2 = 1.
Prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met).
Once the MPR is enabled, any subsequent RD or RDA commands will be redirected to the Multi Purpose
Register. The resulting operation, when a RD or RDA command is issued, is defined by MR3 bits A[1:0] when
the MPR is enabled as shown in table 11. When the MPR is enabled, only RD or RDA commands are allowed
until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2 = 0). Note that in MPR mode
RDA has the same functionality as a READ command which means the auto precharge part of RDA is ignored.
Power-Down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable mode.
The RESET function is supported during MPR enable mode.
Table 19. MPR MR3 Register Definition
MR3 A[2]
MR3 A[1:0]
Function
MPR
0b
1b
MPR-Loc
Normal operation, no MPR transaction.
Don’t care (0b or 1b) All subsequent Reads will come from DRAM array.
All subsequent Write will go to DRAM array.
See the table11
Enable MPR mode, subsequent RD/RDA commands defined by
MR3 A[1:0].
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